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Opteron 6300 Series Käyttöopas
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List of Tables
Table of Contents
Revision History
Table Arithmetic and Logic Operators
Table CPUID Values for AMD Family
Table CPUID Values for AMD Family
Table Supported Mixed Revision Configurations
Table Cross Reference of Product Revision to OSVW ID
Product Errata
Table Cross-Reference of Processor Revision to Errata
Table Cross-Reference of Errata to Package Type
Table Cross-Reference of Errata to Processor Segments
Breakpoint Due to an Instruction that Has an Interrupt
APIC Task-Priority Register May be Incorrect
Corrected L Errors May Lead to System Hang
Scrub Rate Control Register Address Depends on Dctcfgsel
Some Lightweight Profiling Counters Stop Counting When
Lightweight Profiling May Not Indicate Fused Branch
Performance Counter for Instruction Cache Misses Does
Performance Counter for Ineffective Software Prefetches
Performance Counter Does Not Count for some Retired Micro-Ops
GART Table Walk Probes May Cause System Hang
Latency Performance Counters Are Not Accurate
Incorrect Memory Controller Operation Due to a
A Far Control Transfer Changing Processor Operating
VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception
Last-Branch Record Enabled May Cause Machine Check
Hypertransport ™ Link Retry Due to Partial CRC Error
Hypertransport ™ Link Frequency Changes May Cause a
P-State Limit Changes May Not Generate Interrupts
Non-Posted Reads May Block Write Dependent on Probe Responses
Small Code Segment Limits May Cause Incorrect Limit Faults
SB-RMI Processor State Accesses May Persistently
SB-RMI Writes May Not be Observed by Processor
Instruction Addresses Near Canonical Address Limit May Cause GP Exception
Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC Save Area
MC STATUS Enable Bit Not Set When Logging Corrected Errors
CPUID Incorrectly Reports Large Page Support in L Instruction TLB
VMCB Interrupt Shadow Status May be Incorrect
APERF May Increase Unpredictably
P-State Limit and Stop Clock Assertion May Cause System Hang
Local Interrupts LINT LINT May Occur While APIC Is
Processor May Generate Incorrect P-State Limit Interrupts
Load Operation May Receive Incorrect Data after Floating-Point Exception
Debug Breakpoint on Misaligned Store May Cause System Hang
SVM Guest Performance Counters May be Inaccurate Due to SMI
Misaligned Page Crossing String Operations May Cause System Hang
Processor May Cache Prefetched Data from Remapped Memory Region
Instructions Performing Read-Modify-Write May Alter
Some Processor Cores May Have Inaccurate Instruction
AM R Six Core Processor May Limit P-State When Core
Northbridge FIFO Read Write Pointer Overlap May Cause
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